RF front-end for intra-band carrier aggregation

ABSTRACT

The method and apparatus described herein address problems associated with conventional wireless receivers configured for intra-band carrier aggregation. The disclosed solution applies the received signal to a single front-end amplifier, which may comprise a low-noise amplifier, and divides the amplified signal into two or more processing paths, where each path is associated with a different local oscillator frequency corresponding to a different reception band. To compensate for the impact of the additional processing paths on the amplifier performance, a negative resistor unit applies a negative resistance to the output of the front-end amplifier when two or more processing paths are active.

The invention disclosed herein generally relates to intra-band carrieraggregation for wireless receivers, and more particularly to wirelessreceivers capable of selectively switching between contiguous intra-bandcarrier aggregation and non-contiguous intra-band carrier aggregation.

BACKGROUND

Traditionally, cellular handset radio receivers are designed to receivea signal modulated to a single carrier frequency. For example, the radioreceiver may comprise a direct-conversion receiver, where an analog anddigital baseband signal processing circuit downconverts the input signalto I and Q baseband signals using two local oscillator (LO) signals,f_(LO,I) and f_(LO,Q), respectively. Both f_(LO,I) and f_(LO,Q) have thesame frequency, which is equal to the carrier frequency of the inputsignal, and a 90° phase difference, which prevents loss of the receivedinformation during processing. The analog and digital baseband signalprocessing circuit further processes the downconverted I and Q signalswith analog and digital baseband circuits to retrieve the wanted signal.

If the wanted signal contains several adjacent frequency channels, theycan in principle be processed with a single radio receiver having asingle front-end amplifier connected to I and Q downconversion mixersfollowed by a single analog and digital baseband I/Q signal processingcircuit as long as the total bandwidth of the wanted signal does notexceed the bandwidth of the receiver. For example, if the wanted signalcontains N frequency channels, and the bandwidth of one channel isf_(BW), the total bandwidth of the wanted signal may be represented byNf_(BW). To minimize the bandwidth used in baseband/IF signalprocessing, and therefore to minimize power dissipation of the wirelessreceiver, the LO signal used to generate f_(LO,I) and f_(LO,Q) should beplaced in the middle of the received signal band. The bandwidth of thedownconverted wanted signal then becomes Nf_(BW)/2. If the wanted signalcontains an even number of channels, each having the same bandwidth, theLO signal can be placed between two adjacent channels and all channelsare processed as in a low-IF receiver. If the wanted signal contains anodd number of received adjacent channels, each having the samebandwidth, the LO signal should have a frequency equal to the centerfrequency of one of the channels, where this channel would be processedlike in a direct-conversion receiver and the other channels would beprocessed as in a low-IF counterpart receiver.

Carrier aggregation refers to the simultaneous wireless reception ofseveral signal channels associated with different frequencies in LongTerm Evolution (LTE) wireless systems. A similar situation existing inGlobal System for Mobile communications (GSM) and High-Speed DownlinkPacket Access (HSDPA) systems is generally referred to using the termsdual carrier or multi-carrier. While the term “carrier aggregation” isgenerally used herein, it will be appreciated that the following alsoapplies to dual-carrier and multi-carrier systems.

Inter-band carrier aggregation refers to carrier aggregation where thewanted signal channels are in different reception bands. In practice, anoff-chip passive radio frequency (RF) bandpass filter is used before thereceiver integrated circuit (IC) to attenuate potential out-of-bandblocking signals to levels that the receiver IC can tolerate. Forinter-band carrier aggregation, a separate off-chip RF filter is neededfor each reception band, where each filter is usually followed by adedicated low-noise amplifier (LNA) or LNA input stage tuned to thatreception band. The bandwidth of the LNA following the off-chip filtermay be insufficient for simultaneous reception of channels at differentreception bands. A separate LO signal having a different frequency istherefore needed for each reception band for signal downconversion. Eachseparate LO signal (I/Q) requires a separate analog and digitalbaseband/IF signal processing circuit. Inter-band carrier aggregationtherefore requires parallel radio receivers, e.g., one receiver chainfor each simultaneously utilized reception band.

Intra-band carrier aggregation refers to carrier aggregation where allwanted signal channels are within a single reception band, e.g., thepassband of one off-chip RF filter. In contiguous intra-band carrieraggregation, there are at least two wanted signal channels and allwanted signal channels are adjacent or next to each other. Innon-contiguous intra-band carrier aggregation, all wanted signalchannels are not adjacent, e.g., there may be space in the frequencydomain between some of the signal channels. There may also be blockingsignals between wanted signal channels.

In intra-band carrier aggregation, a single off-chip RF filter and oneLNA are generally sufficient because all wanted channels are within thepassbands of the filter and LNA, e.g., two or more channels can bereceived using one RF IC input (single-ended or balanced). For example,assume f_(BW,L) represents the RF bandwidth of the wanted signal channelat the lowest carrier frequency of f_(C,L), and f_(BW,H) represents theRF bandwidth of the wanted signal channel at the highest carrierfrequency of f_(C,H). The total bandwidth of the wanted signal may berepresented by:f _(BW,TOT) =f _(C,H) −f _(C,L)+(f _(BW,H) +f _(BW,L))/2.  (1)It will be appreciated that there may be “empty” channels between thetwo mentioned channels. If f_(BW,TOT)/2 is less than or equal to themaximum available bandwidth of the baseband/IF analog and digital signalprocessing circuits of the receiver, the contiguous and non-contiguousintra-band carrier aggregation may be implemented with a single radioreceiver utilizing only one LO signal. The different wanted channels areseparated/detected in practice in the digital back-end.

If, however, f_(BW,TOT)/2 exceeds the maximum available bandwidth of thebaseband/IF analog and digital signal processing circuits, a singlereceiver chain is not sufficient for contiguous or non-contiguousintra-band carrier aggregation. Further, if blocking signals, which canexist in the frequency bands between the non-contiguous wanted signalchannels, have power levels that cannot be tolerated in the analogand/or digital signal processing circuits of the receiver, a singlereceiver chain is not sufficient for non-contiguous intra-band carrieraggregation. In these cases, the signal processing must be divided inthe frequency domain into two or more parallel chains, which requiresthat the signal be downconverted in parallel I/Q mixers using at leasttwo LO signals with different frequencies. As a result, the receivedsignal must be divided into two or more parallel chains before beingapplied to the downconversion mixers.

A straightforward option is to use two parallel receiver ICs and connectthem to the same RF input. Another option is to use two separatereceivers on the same IC and connect them in parallel to the same RFinput. Both examples require two parallel LNAs. Because LNAs typicallyuse on-chip inductors, which require large silicon area, using two ormore parallel LNAs requires a significant amount of silicon area. Inaddition, the RF input of the receiver IC has to be matched withsufficient accuracy to a specific impedance level, usually 50Ω, becausethe LNA input impedance affects the frequency response of the precedingoff-chip RF filter. The LNA input has to be matched in all modes ofoperation, including when there is only one active LNA or when there aretwo or more parallel LNAs. In addition, the noise figure (NF) of allactive LNAs must meet the same requirements, which sets the requirementsfor the minimum size and bias current of amplifying transistors of theLNAs. The requirements for sufficient input matching and NF regardlessof the number of parallel LNAs means that the number of parallel devicesconnected to the RF input increases relative to the case where only oneLNA is used in all modes of receiver operation. The higher number ofparallel input devices means higher parasitic capacitances at thereceiver RF input, which causes problems with input matching and/or theneed for additional off-chip matching components. Using multipleparallel LNAs also significantly increases the supply current of the RFfront-end. Thus, the use of parallel LNAs in parallel receivers is notdesirable, especially if they use off- or on-chip inductors.

Another solution uses a single LNA capable of amplifying all wantedinput signal channels in intra-band carrier aggregation, and thendividing the signal chain into two or more parallel signal processingchains. In the following it is assumed that the LNA is followed by apassive current-mode I/O downconversion mixer, and the resistive inputimpedance of the mixer forms part of the LNA load impedance. Thedivision of one signal chain into two parallel chains may be implementedby connecting the inputs of two passive current-mode I/Q mixers to theLNA output. The use of parallel passive current-mode I/Q mixersmaintains high linearity because highly linear circuit blocks are placedin parallel. However, when multiple passive I/Q mixers are connected tothe LNA output, the LNA load impedance decreases relative to the casewhere only one I/Q mixer is connected to the LNA output. The LNA may usefeedback from the node where the parallel I/Q mixers are connected. Forexample, when the LNA comprises a resistive-feedback LNA, the LNAperformance parameters (like gain, input matching, and NF) maydeteriorate. When another passive current-mode I/Q mixer is connected tothe LNA output, the LNA output signal current is divided between the twoparallel passive I/Q mixers, which means that the signal gain (oreffective transconductance) provided by the RF front-end decreases,which leads to higher receiver NF. One way to address this problem is toincrease the equivalent transconductance in the LNA, which in practiceincreases the LNA power consumption and/or the parasitic capacitances inthe LNA. Unfortunately, larger parasitic capacitances may deterioratethe LNA input matching and NF, and lower the maximum frequency ofoperation. Moreover, the higher power consumption of such a solution isundesirable in portable devices.

Thus, alternate solutions are needed in the RF front-end for enablingintra-band carrier aggregation when processing the received signalrequires using two or more separate LO signals with differentfrequencies.

SUMMARY

The method and apparatus described herein provide a solution thataddresses the above-described problems associated with wirelessreceivers configured for conventional intra-band carrier aggregation.Broadly, the solution involves applying the received signal to a singlefront-end amplifier, which may comprise a low-noise amplifier, anddividing the amplified signal into two or more processing paths, whereeach path is associated with a different local oscillator frequencycorresponding to a different reception channel or channels. Tocompensate for the impact of the additional processing paths on theamplifier performance, a negative resistor unit applies a negativeresistance to the output of the front-end amplifier when two or moreprocessing paths are active.

One exemplary embodiment provides a wireless receiver configured forintra-band carrier aggregation, where the receiver comprises a front-endamplifier, two or more processing chains, a negative resistor unit, anda selection unit. The front-end amplifier operates at one or more radiofrequencies. The processing chains are connected in parallel at a commonnode, where the common node operatively connects to an output of thefront-end amplifier, and wherein each of the two or more processingchains operate with a different local oscillator frequency. The negativeresistor unit selectively operatively connects to the common node. Theselection unit is configured to enable the negative resistor unit toapply a first negative resistance to the output of the front-endamplifier when two or more of the processing chains are active during amultiple frequency mode, where the multiple frequency mode is associatedwith multiple different local oscillator frequencies. During a singlefrequency mode, when only one of the two or more processing chains isactive, the selection unit may further operatively disable the negativeresistor unit such that the negative resistor unit does not affect theamplifier performance.

Another exemplary embodiment provides a method of controlling a gain ofa wireless receiver configured for intra-band carrier aggregation, wherethe receiver includes a front-end amplifier operating at one or moreradio frequencies, two or more processing chains connected in parallelat a common node, where the common node operatively connects to anoutput of the front-end amplifier and each of the processing chainsoperates with a different local oscillator frequency, and a negativeresistor unit selectively operatively connected to the common node. Themethod comprises enabling the negative resistor unit when two or more ofthe processing chains are active in a multiple frequency mode to apply afirst negative resistance to the output of the front-end amplifier,where the multiple frequency mode is associated with multiple differentlocal oscillator frequencies. During a single frequency mode, when onlyone of the two or more processing chains is active, the method mayfurther operatively disable the negative resistor unit such that thenegative resistor unit does not affect the amplifier performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a block diagram of a wireless receiver according to oneexemplary embodiment.

FIG. 2 depicts a block diagram for an exemplary processing chain.

FIGS. 3A-3B depict exemplary mixers applicable for the processing chainof FIG. 2.

FIG. 4 depicts an exemplary method implemented by the wireless receiverof FIG. 1.

FIGS. 5A-5C depict circuit diagrams for different exemplaryimplementations of the negative resistor unit of FIG. 1.

FIG. 6 depicts an exemplary circuit diagram for portions of oneexemplary wireless receiver.

DETAILED DESCRIPTION

FIG. 1 depicts a wireless receiver 100 according to one exemplaryembodiment. Receiver 100 incorporates a negative resistor unit 140 witha conventional receiver design to compensate for the amplifier gain lossthat may occur when the receiver 100 uses multiple active processingchains associated with multiple different local oscillator frequenciesfor intra-band carrier aggregation.

Receiver 100 comprises an antenna 105, filter 110, RF front-endamplifier 120, a plurality of processing chains 130 ₁, . . . 130 _(N),generally referred to herein as processing chains 130, a negativeresistor unit 140, and a selection unit 150. The antenna 105 and filter110 are generally off-chip from the other receiver components, which aregenerally arranged on a single integrated circuit chip.

Filter 110 comprises a pre-selection filter 110 that pre-selects thereceived RF band from the signal received by antenna 105. RF front-endamplifier 120, which may comprise a low noise amplifier (LNA) operatingat RF, amplifies the RF signal output by filter 110 for furtherprocessing in one or more of the processing chains 130. Amplifier 120may be realized using any known implementation, including but notlimited to, an inductively-degenerated common-source amplifier,resistively-feedback amplifier, etc. While not explicitly shown in FIG.1, amplifier 120 may have differential inputs and outputs. A localoscillator 160 (FIG. 2) outputs a local oscillator signal for eachprocessing chain 130. For example, a local oscillator 160 outputsf_(LO1) to processing chain 130 ₁. It will be appreciated that eachprocessing chain 130 may have its own local oscillator 160, that asingle local oscillator 160 may generate all of the different localoscillator signals for each processing chain 130, or that a single localoscillator 160 may generate the local oscillator signals for some of theprocessing chains, while one or more additional local oscillator(s) 160may generate the local oscillator signal for the remaining processingchains 130. In any event, each active processing chain 130 outputs adifferent processed digital signal OUT_(n) associated with a differentlocal oscillator signal.

While not explicitly shown in FIG. 1, it will be appreciated that eachprocessing chain 130 may comprise an In-Phase and Quadrature path, whichprocess the amplified RF signal to respectively generate a digitalIn-phase and Quadrature signal, e.g., at baseband or IF, responsive tothe corresponding local oscillator frequency, and which are subsequentlycombined to generate a digital output signal OUT_(n) for thecorresponding processing chain, where n=1, 2, . . . N FIG. 2 shows oneexemplary processing chain 130 that may be used in receiver 100comprising an optional resistor 132, In-phase and Quadrature mixers 164,analog processor 136, and digital processor 138. Local oscillator 160outputs a local oscillator signal to phase shift unit 162, whichgenerates Quadrature phases for the local oscillator signals of theQuadrature and In-phase processing chains such that f_(LO,Q) provided tothe Quadrature processing chain is 90° out-of-phase with f_(LO,I)provided to the In-phase processing chain.

While not required, mixers 164 preferably comprise passive current-modeMOSFET mixers, which ideally produce no flicker noise and provide highlinearity. While not explicitly shown in FIG. 2, mixers 164 may befollowed by transimpedance amplifiers and/or buffers, e.g., as shown inFIG. 6, to provide proper current-mode mixing operation. FIGS. 3A and 3Bdepict exemplary passive current-mode MOSFET mixers 164, where the mixer164 of FIG. 3A comprises a single-balanced passive current-mode MOSFETmixer and the mixer 164 of FIG. 3B comprises a double-balanced passivecurrent-mode MOSFET mixer. While not explicitly shown in FIGS. 3A-3B,additional components are generally included after the passive currentmode mixers 164 to facilitate proper current-mode mixing operation,e.g., transimpedance amplifiers and/or buffers at the output nodes.

The amplified In-phase (I_(a)) and Quadrature (Q_(a)) signals areapplied to the analog processor 136, which processes the In-phase andQuadrature signals and converts the resulting I and Q analog signals toa digital In-phase signal I_(d) and a digital Quadrature signal Q_(d),e.g., at baseband or IF. Digital processor 138 digitally processes thedigital In-phase and Quadrature signals to generate the output signalfor that processing chain 130, e.g., OUT₁.

As previously mentioned, loading the amplifier output with two or moreactive parallel processing chains 130 decreases the amplifier loadimpedance relative to the case when the amplifier output is applied toonly one active processing chain 130, which may deteriorate amplifierperformance parameters, e.g., gain, input matching, noise figure, etc.More particularly, when more than one active processing chain 130 isconnected to the amplifier output, the amplifier output signal currentis divided between the multiple parallel processing chains 130, whichreduces the gain or effective transconductance from the input ofamplifier 120 to an output of downconversion mixer 164, and thereforeincreases the noise figure. The selection unit 150 compensates for thiseffect by enabling the negative resistor unit 140 to add a negativeresistance between the common node 122 connecting the input of theparallel processing chains 130 and ground when more than one of theprocessing chains 130 is active.

FIG. 4 shows an exemplary method 200 implemented by the selection 150.When the selection unit 150 determines more than one processing chain130 is active for a multiple frequency mode (block 210), the selectionunit 150 enables the negative resistor unit 140 to apply the desirednegative resistance R_(NEG) to the amplifier output (block 230), wherethe applied negative resistance is variable and depends on the number ofactive processing chains 130 and/or an effective input impedance of theadditional processing chains 130. However, when the selection unit 150determines only one processing chain 130 is active for a singlefrequency mode (block 210), the selection unit 150 operatively disablesthe negative resistor unit 140 (block 220).

As used herein, “operatively disable” refers to controlling the negativeresistor unit 140 during the single frequency mode such that thenegative resistor unit does not substantially affect the amplifier gain,noise figure, or other amplifier performance parameters. For example,the selection unit 150 may operatively disable the negative resistorunit 140 by disabling the negative resistor unit 140 such that no DCcurrent flows through the negative resistor unit 140 and the negativeresistor unit 140 has a negligible effect on the front-end amplifierperformance. This embodiment has the additional advantage of providingpower savings during the single frequency mode. Alternatively, theselection unit 150 may operatively disable the negative resistor unit140 by enabling the negative resistor unit 140 such that the negativeresistance applied to the amplifier output has a much higher absolutevalue than the negative resistance applied during the multiple frequencymode. For example, during the single frequency mode the negativeresistor unit 140 may apply a negative resistance having an absolutevalue that is at least three times the absolute value of the negativeresistance applied during the multiple frequency mode, or is at least500Ω. According to still another embodiment, the selection unit 150 mayoperatively disable the negative resistor unit 140 by disconnecting theenabled negative resistor unit 140 from node 122 such that the negativeresistor unit 140 connects to another amplifier connection point, e.g.,an amplifier power supply. In this embodiment, the negative resistancemay be the same or different than that associated with the multiplefrequency mode.

The following provides additional details describing the effect of thenegative resistor unit 140, e.g., in FIG. 1, when enabled. If thevoltage at node 122 is ν_(A) and the current from node 122 to groundthrough negative resistor unit 140 is i_(A,gnd), the resistance ofnegative resistor unit 140 may be represented by−R_(NEG)=ν_(A)/i_(A,gnd)<0Ω. When only one processing chain 130 isactive, the impedance seen from the output of amplifier 120 may berepresented by R_(load)=R_(pc1), where R_(pc1) represents the inputimpedance of processing chain 130 ₁. However, when two processing chains130 are active, the impedance seen from the output of amplifier 120 maybe represented by the parallel combinationR′_(load)=R_(pc1)∥R_(pc2)∥(−R_(NEG)), where R_(pc2) represents the inputimpedance of processing chain 130 ₂. It will be appreciated that R_(pc1)does not need to equal R_(pc2). If −R_(NEG)=−R_(pc2),R′_(load)=R_(load), which means that the amplifier performance (e.g.,input matching, gain, etc.) stays relatively the same as compared to thesingle frequency mode, and the voltage gain from the RF input to theoutput of the processing chains 130 remains essentially the same.Similar logic applies when more than two processing chains 130 areactive.

The implementation of a negative resistance requires active components.For example, FIGS. 5A-5C depict exemplary negative resistor units 140.FIGS. 5A and 5B depict a single-ended and differential implementation,respectively, using transconductance amplifiers. The negative resistorunit 140 of FIG. 5A comprises a single-ended transconductance amplifierconfigured in a feedback mode such that the V₁ node selectively couplesto node 122. The input resistance of the circuit of FIG. 5A may berepresented by V₁/I₁=−1/g_(m). Thus, the circuit of FIG. 5A realizes anegative resistance when enabled, where the value of the negativeresistance depends on, for example, the bias current, the sizes of thedevices, e.g., the transistors and resistors, and the topology of thenegative resistor circuit. FIG. 5B depicts a balanced differentialcircuit achieved when two transconductance amplifiers, e.g., those ofFIG. 5A, are differentially connected, where the differential nodes (V₁₊and V¹⁻) connect to differential amplifier outputs. In this example, theinput resistance may be represented byV₁/I₁=(V₁₊−V¹⁻)/(I₁₊−I¹⁻)=−1/g_(m). The negative resistance of thenegative resistor unit 140 is varied according to the number of activeprocessing chains 130. This may be implemented, for example, by changingthe value of a bias current or voltage in the negative resistor unit140. Another option uses matrices of parallel- or series-connecteddevices instead of single devices in the negative resistor unit 140, andto switch on/off the devices in the component matrices to control thevalue of the negative resistance. It is also possible to use a negativeresistor unit 140 comprising parallel negative resistor circuits, wherethe number of active negative resistor circuits depends on the number ofactive processing chains 130.

FIG. 5C depicts another exemplary negative resistor unit 140 comprisinga cross-coupled common-source transistor stage (M₁, M₂) with resistivedegeneration (R_(S1), R_(S2)) to improve linearity. In this embodiment,the negative resistance is derived based on the transconductance of M₁and M₂ and the resistances of the R_(S1) and R_(S2). It will beappreciated, however, that R_(S1) and R_(S2) are optional; when omittedthe negative resistance is derived based on the transconductance of M₁and M₂ at the expense of lower linearity. Resistors R_(B1) and R_(B2)comprise bias resistors set to a large value at the frequency ofoperation. In FIG. 5C, V_(B) represents a bias voltage for the negativeresistor unit 140, where V_(B) is coupled to the gates of thetransistors M₁, M₂ so as to enable/disable the negative resistor unit140 and control the negative resistance. For example, the negativeresistor unit 140 may be enabled by setting V_(B) to a value greaterthan a threshold, and may be disabled by setting V_(B) to a value lessthan the threshold, e.g., 0 V. While FIG. 5C shows an embodiment using abias voltage to enable/disable the negative resistor unit 300, thoseskilled in the art will appreciate that any type of bias signal, e.g., abias current, etc., could be used to enable/disable the negativeresistor unit 140. When enabled, the negative resistance of the negativeresistor unit 140 of FIG. 5C may be approximated as:

$\begin{matrix}{{{- R_{NEG}} = {{- \left( {\frac{1}{g_{m\; 1}} + R_{S}} \right)} \approx {- R_{S}}}},} & (2)\end{matrix}$where g_(m), represents the transconductance of transistor M₁, R_(S)represents the value of degeneration resistors (R_(S)=R_(S1)=R_(S2)),and the approximation holds if g_(m1)R_(S)>>1. In this example, theabsolute value of the resistance of the negative resistor unit 140should track the input resistance of the mixer in the additionalprocessing chain(s) 130, e.g., processing chain 130 ₂ to minimize gainvariations. In other words, when two processing chains are active, thenegative resistor unit 140 should be configured such that the negativeresistance generally equals the negative of one of the processing chaininput impedances, e.g., −R_(NEG)=−R_(pc,2) regardless of supply voltage,temperature, operational frequency, etc. If R_(pc,2) depends mostly onthe value of the resistors in series with mixer switching transistors,R_(S1) and R_(S2) should be implemented using the same resistormaterial. The bias voltage V_(B) can be controlled in such a way thatthe effective amplifier transconductance g_(m) also tracks the resistormaterial. Another possibility is to build a bias circuit that controlsthe value of V_(B) in such a way that the value of g_(m) tracks theon-resistance of the mixer switching transistors. The negative resistorunit 140 adds parasitic capacitance to the output of the front-endamplifier 120. If problematic, this parasitic capacitance may be tunedout at the frequency of interest, taking the LNA load inductor intoaccount, by decreasing the amplifier load capacitance by thecorresponding amount, if possible, and if not, by reducing the amplifierload inductance by a suitable amount to enable a higher total amplifierload capacitance.

FIG. 6 depicts exemplary circuit details for the amplifier and analogprocessor of the wireless receiver and processing chain of FIGS. 1 and2. In this embodiment, a baseband amplifier couples to the output ofeach passive current-mode mixer 164, where the baseband amplifiercomprises a transimpedance amplifier (TIA) 170 that uses operationalamplifiers at analog baseband to realize a virtual ground at the mixeroutput, which may improve the linearity of mixer 164. The transimpedanceamplifiers 170 are, for example, part of the analog processor 136.

The ability to selectively activate one or more processing chains 130while maintaining the performance of the front-end amplifier 120 using anegative resistor unit 140 provides several advantages. First, thenegative resistor unit 140 addresses the amplifier performance issueswhile consuming less current than conventional solutions, whichgenerally have higher power consumption due to the increase in theamplifier transconductance. Further, the solution disclosed hereincompensates for the addition of another processing chain 130 to thesignal chain at the node where the addition occurs, which minimizes thenumber of circuit blocks that have to be modified between single andmultiple frequency modes. Further still, the solution disclosed hereinremoves the need to implement additional configurability in thefront-end amplifier 120. This is beneficial because the performance ofthe front-end amplifier 120 is sensitive to parasitic effects, e.g.,parasitic capacitances, and adding more configurability to the amplifier120 usually results in an increase in the number of transistors, whichin turn increases the parasitic capacitances. This can affect, forexample, the amplifier noise figure (NF), input matching, linearity, andavailable bandwidth of operation. In direct contrast, with the solutiondisclosed herein, the amplifier configuration remains the same in thesingle frequency mode and the multiple frequency mode. In addition, thesolution disclosed herein may be used with any amplifier topology, forexample, common-gate, inductively-degenerated common-source, andresistive-feedback amplifier topologies. Further still, the increase inthe noise figure associated with the solution disclosed herein isinsignificant. More particularly, the implementation of the solutiondisclosed herein slightly increases the noise figure and decreases thelinearity, but the noise figure and linearity remain sufficient forpractical applications, particularly when considered in light of theprovided benefits. It will further be appreciated that the increase insilicon area associated with the solution disclosed herein is small.

The present invention may, of course, be carried out in other ways thanthose specifically set forth herein without departing from essentialcharacteristics of the invention. The present embodiments are to beconsidered in all respects as illustrative and not restrictive, and allchanges coming within the meaning and equivalency range of the appendedclaims are intended to be embraced therein.

What is claimed is:
 1. A wireless receiver configured for intra-bandcarrier aggregation, the receiver comprising: a front-end amplifieroperating at one or more radio frequencies; two or more processingchains connected in parallel at a common node, said common nodeoperatively connected to an output of the front-end amplifier, whereineach of said two or more processing chains operate with a differentlocal oscillator frequency; a negative resistor unit selectivelyoperatively connected to the common node; and a selection unitconfigured to enable the negative resistor unit to apply a firstnegative resistance to the output of the front-end amplifier when two ormore of said processing chains are active during a multiple frequencymode, said multiple frequency mode associated with multiple differentlocal oscillator frequencies.
 2. The receiver of claim 1 wherein theselection unit is further configured to disable the negative resistorunit when only one of said two or more processing chains is activeduring a single frequency mode associated with a single local oscillatorfrequency.
 3. The receiver of claim 1 wherein the selection unit isfurther configured to operatively disable the negative resistor unitwhen only one of said two or more processing chains is active during asingle frequency mode associated with a single local oscillatorfrequency.
 4. The receiver of claim 3 wherein the selection unitoperatively disables the negative resistor unit by enabling the negativeresistor unit such that a second negative resistance is applied to theoutput of the front-end amplifier, wherein an absolute value of saidsecond negative resistance is sufficiently larger than an absolute valueof the first negative resistance such that the second negativeresistance has a negligible effect on a gain of the front-end amplifier.5. The receiver of claim 4 wherein the absolute value of the secondnegative resistance is at least three times greater than the absolutevalue of the first negative resistance.
 6. The receiver of claim 4wherein the absolute value of the second negative resistance is greaterthan or equal to 500Ω.
 7. The receiver of claim 3 wherein the selectionunit operatively disables the negative resistor unit by disconnectingthe negative resistor unit from the common node and connecting thenegative resistor unit to an alternate connection point in the front-endamplifier.
 8. The receiver of claim 7 wherein the alternate connectionpoint comprises an amplifier power supply.
 9. The receiver of claim 1wherein the negative resistance of the enabled negative resistor unit isvariable and depends on the number of processing chains.
 10. Thereceiver of claim 1 wherein each processing chain comprises: an I/Qmixer configured to downconvert a radio frequency signal at the outputof the front-end amplifier responsive to a corresponding localoscillator frequency to generate analog In-phase and Quadrature signalsat corresponding intermediate or baseband frequencies; an analog signalprocessor configured to process the analog In-phase and Quadraturesignals at the corresponding intermediate or baseband frequencies togenerate digital In-phase and Quadrature signals; and a digital signalprocessor configured to process the digital In-phase and Quadraturesignals.
 11. The receiver of claim 10 wherein each I/Q mixer comprises apassive current-mode MOSFET mixer.
 12. The receiver of claim 10 whereineach analog signal processor comprises a transimpedance amplifieroperatively coupled to an output of the corresponding I/Q mixer andconfigured to form a virtual ground or low impedance termination at theoutput of the corresponding I/Q mixer.
 13. The receiver of claim 1wherein the first negative resistance compensates for changes in aneffective load impedance of the front-end amplifier when applied to theoutput of the front-end amplifier during the multiple frequency mode,such that the gain of the front-end amplifier in the multiple frequencymode generally equals the gain of the front-end amplifier in a singlefrequency mode.
 14. The receiver of claim 1 wherein the negativeresistor unit comprises one of a single-ended negative resistorconfiguration and a differential negative resistor configuration. 15.The receiver of claim 14 wherein the differential negative resistorconfiguration comprises cross-coupled common source transistors, eachhaving a transconductance, and each controlled by a bias input to eachgate of the common source transistors, and wherein the negativeresistance of the enabled negative resistor unit is derived based on thetransconductances of the common-source transistors.
 16. The receiver ofclaim 15 wherein the differential negative resistor configurationfurther comprises one or more degeneration resistors coupled to thesource of each transistor, wherein the negative resistance of theenabled resistor unit is further derived based on the resistances of theone or more degeneration resistors.
 17. The receiver of claim 15 whereinthe selection unit is configured to enable the negative resistor unit toapply the first negative resistance by setting the bias to a first valuegreater than a threshold.
 18. The receiver of claim 1 wherein thereceiver is configured for one of contiguous intra-band carrieraggregation and non-contiguous intra-band carrier aggregation.
 19. Thereceiver of claim 1 wherein the front-end amplifier comprises alow-noise amplifier.
 20. A method of controlling a gain of a wirelessreceiver configured for intra-band carrier aggregation, said receivercomprising a front-end amplifier operating at one or more radiofrequencies, two or more processing chains connected in parallel at acommon node, said common node operatively connected to an output of thefront-end amplifier and each of said two or more processing chainsconfigured to operate with a different local oscillator frequency, and anegative resistor unit selectively operatively connected to the commonnode, the method comprising: determining whether the receiver isconfigured for a single frequency mode associated with a single localoscillator frequency or a multiple frequency mode associated withmultiple local oscillator frequencies; and enabling the negativeresistor unit when two or more of the processing chains are active forthe multiple frequency mode to apply a first negative resistance to theoutput of the front-end amplifier, each of said multiple different localoscillator frequencies of the multiple frequency mode associated with adifferent one of the active processing chains.
 21. The method of claim20 further comprising disabling the negative resistor unit when only oneof the two or more processing chains is active for the single frequencymode, wherein the single local oscillator frequency is associated withthe active processing chain.
 22. The receiver of claim 20 furthercomprising operatively disabling the negative resistor unit when onlyone of said two or more processing chains is active during the singlefrequency mode associated with a single local oscillator frequency. 23.The receiver of claim 22 wherein operatively disabling the negativeresistor unit comprises enabling the negative resistor unit such that asecond negative resistance is applied to the output of the front-endamplifier, wherein an absolute value of said second negative resistanceis sufficiently larger than an absolute value of the first negativeresistance such that the second negative resistance has a negligibleeffect on a gain of the front-end amplifier.
 24. The receiver of claim23 wherein the absolute value of the second negative resistance is atleast three times greater than the absolute value of the first negativeresistance.
 25. The method of claim 23 wherein the absolute value of thesecond negative resistance is greater than or equal to 500 Ω.
 26. Themethod of claim 22 wherein operatively disabling the negative resistorunit comprises disconnecting the negative resistor unit from the commonnode and connecting the negative resistor unit to an alternateconnection point in the front-end amplifier.
 27. The method of claim 26wherein the alternate connection point comprises an amplifier powersupply.
 28. The method of claim 20 further comprising setting thenegative resistance of the negative resistor unit based on the number ofactive processing chains.
 29. The method of claim 20 further comprisingsetting the negative resistance of the negative resistor unit based onan effective input impedance of the multiple active processing chains.30. The method of claim 20 wherein each processing chain is configuredto: downconvert the radio frequency signal at the output of thefront-end amplifier responsive to a corresponding local oscillatorfrequency to generate analog In-phase and Quadrature signals atcorresponding intermediate or baseband frequencies in an I/O mixer;process the analog In-phase and Quadrature signals at the correspondingintermediate or baseband frequencies to generate digital In-phase andQuadrature signals in an analog signal processor; process the digitalIn-phase and Quadrature signals in a digital signal processor; and themethod further comprising configuring the analog signal processor toform a virtual ground or low impedance termination at the output of thecorresponding I/Q mixer.
 31. The method of claim 20 wherein enabling thenegative resistor unit comprises enabling the negative resistor unitsuch that the negative resistance compensates for changes in aneffective load impedance of the front-end amplifier when the second oradditional one of the two or more of the processing chains are activesuch that the gain of the front-end amplifier in the multiple frequencymode generally equals the gain of the front-end amplifier in the singlefrequency mode.
 32. The method of claim 20 wherein the negative resistorunit comprises a pair of cross-coupled common-source transistorscontrolled by a bias input to each gate of the common sourcetransistors, wherein enabling the negative resistor unit comprisessetting the bias to a first value greater than a threshold.
 33. Themethod of claim 20 wherein the receiver is configured for one ofcontiguous intra-band carrier aggregation and non-contiguous intra-bandcarrier aggregation.